Link Layer interrupt status register
| DSM_ENTERED_INTR | On a firmware request to LL to enter into state machine, working on LF clock, LL transitions into Deep Sleep Mode and asserts this interrupt. The interrupt can be cleared by writing one into this location. |
| DSM_EXITED_INTR | On a firmware request to LL to exit from Deep Sleep Mode, working on LF clock, LL transitions from Deep Sleep Mode and asserts this interrupt when the Deep Sleep clock gater is turned ON. The interrupt can be cleared by writing one into this location. |
| RCBLL_DONE_INTR | RCB transaction Complete |
| BLERD_ACTIVE_INTR | CYBLERD55 is in active mode. RF is active |
| RCB_INTR | RCB controller Interrupt - Refer to RCB_INTR_STAT register |
| LL_INTR | LL controller interrupt - Refer to EVENT_INTR register |
| GPIO_INTR | GPIO interrupt |
| EFUSE_INTR | This bit when set by efuse controller logic when the efuse read/write is completed |
| XTAL_ON_INTR | enabled crystal stable signal rising edge interrupt. The interrupt can be cleared by writing one into this location. |
| ENC_INTR | Encryption Interrupt Triggered |
| HVLDO_LV_DETECT_POS | This interrupt is set on HVLDO LV Detector Rise edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output |
| HVLDO_LV_DETECT_NEG | This interrupt is set on HVLDO LV Detector Fall edge. There is a 1cycle AHB clock glitch filter on the HVLDO LV Detector output |